1. Field of the Invention
The present invention relates to a defect inspection method for inspecting a defect of a semiconductor wafer.
2. Description of the Background Art
In a method for controlling the quality and managing and improving the yield rate of a semiconductor wafer (hereinafter simply referred to as “wafer”) in a semiconductor wafer process, it is essential to inspect a defect of the wafer in a main or important step included in the semiconductor wafer process, to thereby identify a foreign material and a defect in the wafer, manage a transition thereof, detect a process step including a problem, give a quick feedback, and the like.
In a semiconductor wafer process composed of a plurality of processes performed by many semiconductor manufacturing apparatuses, a defect that may adversely influence the characteristics occurs on a wafer during the preparation of a device (a chip obtained as a result of singulating the wafer) because of, for example, a foreign material existing in a clean room or in the apparatus used for each process, a damage to the wafer caused by performing many processes thereon, a pattern failure occurring in the formation of a pattern on the wafer, or the like. Such a defect causes a deterioration in the yield rate.
Additionally, in a wafer (such as a silicon carbide wafer (hereinafter also referred to as “SiC wafer”) and a gallium nitride wafer (hereinafter also referred to as “GaN wafer”)) having an inferior quality in which many substrate defects are contained, not all the defects cannot be detected and screened by a defect inspection included in the semiconductor wafer process, and there is a high possibility that some defects cannot be found by the detection. Therefore, a problem arises that an excessive burden is imposed on subsequent steps such as a testing step and a reliability evaluation step (that is, conditions required to be satisfied in these steps become excessively high), which greatly loweres the efficiency. In this manner, in a case where a wafer such as a SiC wafer and a GaN wafer having an inferior quality in which many defects are contained in the wafer itself is used in the semiconductor wafer process, the defects of the wafer itself may adversely influence the device characteristics. This causes a deterioration in the yield rate.
Moreover, if a wafer (device) having a defect that may influence the device characteristics cannot be selected in an electrical characteristics test and its failure is determined for the first time in a subsequent reliability test so that the wafer is selected at that time, time and labor are wastefully consumed for the failure device because the failure device has been formed through many processes. This causes an inefficiency in an inspection step of evaluating the electrical characteristics and the like.
Conventionally, there is a technique of inspecting the presence or absence of a defect on the wafer and marking a position where the defect is detected to thereby determine the good/poor of the device (for example, see Japanese Patent Application Laid-Open No. 63-222438 (1988)).
To improve the yield rate in the semiconductor wafer process, it is necessary that a defect of a wafer or a defect in each process that may influence the device characteristics is detected with a sufficient accuracy and then, based on a result of the detection, the wafer is rejected at an early stage or a feedback is given to the process in which the defect has occurred, in order to reduce defects. For this purpose, it is desirable that defect information obtained as a result of a defect inspection is grasped as electronic data on a chip basis.
In Japanese Patent Application Laid-Open No. 63-222438 (1988), a result obtained by a defect inspection is not dealt as electronic data. Moreover, the defect inspection is not performed on the wafer itself having an inferior quality mentioned above. Therefore, there is a possibility that a defect of the wafer itself adversely influences the device characteristics and causes a deterioration in the yield rate.